A standard ECL output gate circuit, illustrated in FIG. 1, includes a pair of ECL gate transistors Q1 and Q2. In this example transistor Q1 provides an input transistor element for receiving input signals of high and low potential. Transistor Q2 provides a reference transistor element to which a reference voltage signal is applied at an intermediate reference voltage level between the high and low potential input signal levels. The emitter terminals of transistors Q1 and Q2 are coupled together at a common emitter node coupling. Current sink I1, coupled between the common emitter node coupling and ground orlow potential GND generates the tail current. The current sink I1 is typically a current source transistor with a tail resistor in its emitter current path generating the tail current. A bias voltage generator, not shown, provides the current source voltage applied to the base current source transistor.
The ECL gate transistors Q1 and Q2 provide alternative current paths through respective collector path swing voltage resistors R2 and R3 which are in turn coupled through common resistor element R1 to the high potential power supply V.sub.cc. Typically, the ECL gate resistor elements R1, R2, and R3 have substantially equal resistance. Current sink I1 generates the ECL gate current in the alternative current paths through swing resistors R2 or R3 according to the input signal V.sub.in at the base of input transistor element Q1.
Typical ECL gates may also be constructed according to the differential signal input configuration. In the differential signal input ECL gate circuit configuration, the gate transistors Q1 and Q2 constitute differential input transistors for differential or complementary inputs V.sub.in and V.sub.in, rather than functioning as input transistor and reference transistor as illustrated in FIG. 1.
As further shown in FIG. 1, complementary ECL gate output signals are taken from the collector nodes of the ECL gate transistors Q1 and Q2. In this example the true output signal OUT or V.sub.o is taken from the collector node of reference transistor Q2. The complementary output signal OUTN or V.sub.o is taken from the collector node of input transistor element Q1. The output signals from the collector nodes of ECL gate transistors Q1 and Q2 are sourced respectively through output buffer emitter follower transistor elements Q3 and Q4 to the respective complementary and true outputs, OUTN and OUT.
The output buffer transistors Q3 and Q4 are coupled in emitter follower configuration between the high potential power supply V.sub.cc and the respective current sinks I2 and I3. The output buffer emitter follower transistor elements Q3 and Q4 provide impedance transformation and matching between the ECL gate and output circuits to which the respective complementary and true outputs OUTN and OUT are coupled.
A disadvantage of the conventional ECL output gate is that each of the output buffer emitter follower transistor elements Q3 and Q4 must source current both to the respective output OUTN or OUT and the respective current sink I2 or I3 when pulling up the output for transition from low to high potential at the output. The output load is therefore deprived of the charging current required to feed the current sink with resulting decrease in switching speed during the low to high transition. During the stationary state or standby condition there is also substantial power dissipation. Furthermore during a high to low transition at the output, the respective current sink I2 or I3 is required to sink both the discharge current from the output load and the sourcing current from the respective emitter follower Q3 or Q4. Because of the limited current sinking capability of current sinks I2 and I3, the discharge time for transition from high to low potential is substantially prolonged.